Dolev 4press - Troubleshooting & Diagnostics
The Test Tree - CRI

Ø CRI

Checks the CRI Board (Standalone).

Ø Card Ack.

Checks all CRI Board Pc I/O address range (310H-31EH exclude 316H-317H): When this test fails, all CRI tests below do not execute in the batch.

Ø PC Buffer

This test checks the buffers that separate between PC <-> 196. It is done with internal loop inside the buffers.

Ø XILINX - Load

Loads CRI.XIL file from the current directory to Xilinx.

Ø Verify

Compares Xilinx data to the file data. Uses the following files: CRI.XIL, 2018MASK.XIL

Ø WCS RAM - Data Bus

Checks WCS RAM Data Bus:

1) Clear address counter.
2) Write pattern of data to address=0.
3) Clear address counter.
4) Read back and compare those data.

Ø WCS RAM - Address Bus

Checks WCS RAM Address Bus for stacked or shorted bits.

Ø WCS RAM- Ramp

Checks WCS RAM by writing Ramp (address = data).

Ø WCS RAM- Random

Checks WCS RAM by writing Random data.

Ø Load&Verify

Loads and Verifies WCS:

1) Load CRI.WCS file from the current directory to WCS RAM.
2) Compare WCS data to the file data.

Ø Code & Data

Checks WCS RAM by 196 Fast Access.

1. Write to Message Buffer (FFC0H) data = 1155H.
2. Load special small CRI_MEM.WCS file to WCS RAM.
3. Verify WCS data to the file data.
4. Activate Fast Reset on 196 for test running.
5. Check WCS RAM using Ramp algorithm from address 2200H to DBFFh Micro Checks from DC00 to FBFFh.
6. Delay 1.5 second for test completion.
7. Read and Analyze Message Buffer:

1155H - Buffer Not updated.
2000H - Test was not completed.
1234H - Test completed OK.

xxxxH - The first bad address returned.

Ø Verif by 196

Micro (196) Compares WCS data to CRI.WCS file data.

Verify process is the same like from Pc, described before.

Because of each reading from the WCS is the opcode, the test takes too much time (50 sec.), so this test is not included in the short batch.

Fail on this test means that there was illegal writing to the WCS Code area, so after the fail WCS is being reloaded automatically and the next test execution might complete with Pass.

Ø I2C Chip

Checks the I2C Chip on CRI:

1. Write patterns to I2C base address.
2. Readback those patterns with mask = 7FH (MSB is not activated).
3. Enter and Verify Chip in Clock Mode.
4. Enter and Verify Chip in Normal Mode.
5. Enable I2C Chip Interrupt and check that:
   - I2C Chip responds to the Interrupt.
   - Bus was released.
   - Data was sent out from I2C.

Ø Timer

Checks the 8254 timer:

1) Check Counter counting from 0-1000.
2) Check that the information supplied to the timer is correct.
3) Check 8 bit internal register by walking '1' patterns.
5) Perform (1) - (4) for all three counters in the timer.

Ø Sim Mstep

Checks that a simulated micro step (USTEPCLK) clock can be produced.

1) Generate EXT_SIM_USTEP and check for USTEPCLK.

Ø Sim Moving

Checks that the MOVING signal can be reset and set.

Ø SIM M.STEP - Micro Step

Checks MICRO STEP clocks with six different N_DIV values. For each value the next steps are been done.

Ø SIM M.STEP - Acc Request

Checks accumulation clocks (ACC_LONG_REQ) with six different M_DIV values. N_DIV = 3.

Ø SIM M.STEP - Stop Cond.

Checks Stop Condition signal (STOPCOND) with six different data address generator values.

Ø SIN&COS RAMS - Data Bus

Checks SIN&COS RAM Data Bus.

Ø SIN&COS RAMS - Address Bus

Checks SIN&COS RAM Address Bus for stacked or shorted bits.

Ø SIN&COS RAMS - Ramp

Checks SIN&COS RAM by writing Ramp (address = data).

Ø SIN&COS RAMS - Random

Checks SIN&COS RAM by writing Random data.

Ø POLARITY RAM - Data Bus

Checks POLARITY RAM Data Bus.

Ø POLARITY RAM - Address Bus

Checks POLARITY RAM Address Bus for stacked or shorted bits.

Ø POLARITY RAM - Ramp

Checks POLARITY RAM by writing Ramp (address = data).

Ø POLARITY RAM - Random

Checks POLARITY RAM by writing Random data.

Ø Pll Clocks

Checks the pll frequency (PLL_CK) trough 8254 timer.

Ø Pll Div Clk.

Checks the pll divided frequency (DIV_PLL_CK) trough 8254 timer.

Ø Mov By Phase

Checks MOVING signal with six different phase counter values.

Ø Real Time Ph

Checks the PHASE_DET signal response.

Ø REAL M.STEP - Micro step

Checks Micro Step clock in real mode. Six different N_DIV value are loaded to generate USTEPCLK clock, the number of clocks in an 1 msec time interval are counted. The base clock is 10MHz from pll.

Ø REAL M.STEP - Acc Request

Checks ACC_LONG_REQ clock in real mode. Six different M_DIV value are loaded to generate USTEPCLK clock, the number of clocks in an 1 msec time interval are counted. The base clock is 10MHz from pll and n counter is program to 10.

Ø REAL M.STEP - Stop Cond.

Checks STOPCOND clock in real mode. Six different start values are loaded to generate USTEPCLK clock, the number of clocks in an 1 msec time interval are counted. The base clock is 10MHz from pll and n counter is program to 10.

Ø Line Clock

Checks the LINECK (Line Xilinx) signal with different EOL (Line Xilinx) values.

*) Interval is 5 msec.

Ø Expose Clock

Checks the EXPCK (Line Xilinx) signal with different SOL (Line Xilinx) values.

*) Interval is 5 msec.

Ø Succ. Lines

Checks the EXPCK (Line Xilinx) signal with different SOL (Line Xilinx) values.

*) Interval is 50 * 5 msec.