Dolev 4press - Troubleshooting & Diagnostics
The Test Tree - STROBE5

Ø Strobe5

Checks the STROBE5 Board (Standalone).

Ø XILINX - Load

Loads STROBE.XIL file from the current directory to Xilinx.

Ø XILINX - Verify

Compares Xilinx data to the file data. Uses the following files:

STROBE.XIL, 2018MASK.XIL 3030MASK.XIL

Ø Card Ack.

Checks all STROBE5 Board Pc I/O address range (280H-2BBH except 288H):

When this test fails, all STROBE5 tests below do not execute in the batch. Because this function is realized in the Xilinx, Pass/Fail of the test depends on loading success.

Ø Clocks

Checks 20 Mhz clock and 8254 PIT:

1. 20 Mhz is divided in INTER Xilinx to:
   1Mhz -> CLK1
   1Khz -> CLK0
   1Khz -> CLK2
2. Signals OUT0 and OUT2 close GATE1, so Counter0 and Counter2 are been checked versus Counter1 (Window).

Ø Stop Spiral

Checks the STOP SPIRAL circuit by simulation:

1. Reset ENC_ENB='0' to avoid STP_SPRL & END_STSPL from CRI.
2. Create CLRL to Reset STPSPRLL in INTER Xilinx.
3. Create SETSPIRALL to Set STPSPRLL.
4. Create CLRL to Reset STPSPRLL.

Ø Correct LUT - Data Bus

Checks LUT RAM Data Bus.

Ø Correct LUT - Address Bus

Checks LUT RAM Address Bus for stacked or shorted bits.

Ø Correct LUT - Ramp

Checks LUT RAM by writing Ramp (address = data).

Ø Correct LUT - Random

Checks LUT RAM by writing Random data.

Ø Micro Contr.

All tests below activate diagnostics programs from the PROM's.

Ø Seq Adrs Bus

Checks the Sequencer Address bus by single step.

1) Clear M(0-8) Counter in ALU_D Xilinx.

2) Increment the Counter by PCLK and Read the MEM(0-7) Bus.

3) Repeat (2) 255 times (ramp on MEM bus).

*) Note that the Sequencer is not activated in this test.

Ø Proms ChkSum

Checks PROMs checksum:

1) Disable Sequencer and Load MAP = 0 (for const. result from U807).

2) Load MEM addresses from 0-255.

3) Read PROM's data and calculate the checksum.

Ø Seq Data Bus

Checks the Sequencer operation by single step.

1) Jump to the known MAP address.

2) Check that the sequencer address is OK.

3) Repeat (1) - (2) for 6 different patterns.

Ø Seq Instruct

Checks the Sequencer ability to perform commands from PROM's.

1) Jump to the specific MAP address.

2) Activate sequencer in single step.

3) For each step analyze the sequencer address.

Ø ALU Data Bus

Checks the ALU Data Bus via YB(0-15) bus.

1) Load data pattern to internal ALU register.

2) Readback and Verify the ALU register data.

3) Repeat (1) - (2) for different patterns.

Ø ALU Register

Checks ALU internal registers (single step).

1) Write Ramp pattern to internal ALU registers.

2) Readback and verify registers through ALU Port B.

3) Readback and verify registers through ALU Port A.

Ø ALU Instruct

Checks ALU logic and arithmetic operations.

1. Load LUT with the values which will be passed to internal reg's.
2. Perform addition operation (R0=R0+R1) until carry activating.
3. Perform XOR SUB and AND operations to registers.
4. Verify that no error occurs during above operations, by analysing bits: ALU_F0~, ALU_F15~, CN_16 and ALUERR~

Ø PLL

i) Initialization steps for all PLL tests:

1) Select PLL to desired frequency range.

2) Select 500KHz to PLL_REF via ENCLK CLK2.

Ø Low Range Frequency

Checks PLL Low Range frequencies (45-130 MHz).

i) PLL tests Initialization.

1) Load CORRECTION LUT:

no Correction (8000H),

no Start of Line Delay (0),

no Expose Delay (4),

no Lock Delay (3).

2) Load Div_N for each frequency.

3) Start Run ALU and Measure EXP_CLK2 -> CLK1.

Ø Low Range Lock Delay

Checks Lock Delay

i) PLL tests Initialization.

1) Load CORRECTION LUT:

no Correction (8000H),

no Start of Line Delay (0),

no Expose Delay (4),

Lock Delay (3-511).

2) Load Div_N for 87.5 Mhz frequency (Resolution=100).

3) Start Run ALU and Measure EXP_CLK2 -> CLK1.

Ø Low Range Expose Delay

Checks Expose Delay

i) PLL tests Initialization.

1) Load CORRECTION LUT:

no Correction (8000H),

no Start of Line Delay (0),

Expose Delay (4-255)

no Lock Delay (3).

2) Load Div_N for 87.5 Mhz frequency (Resolution=100).

3) Start Run ALU and Measure EXP_CLK2 -> CLK1.

Ø Low Range Accumulation

Checks the Accumulative Correction factor

i) PLL tests Initialization.

1) Load CORRECTION LUT:

Correction=8000H (no correction), 4000H, C000H

no Start of Line Delay (0),

no Expose Delay (4),

no Lock Delay (3).

2) Load Div_N for 87.5 Mhz frequency (Resolution=100).

3) Start Run ALU and Measure EXP_CLK2 -> CLK1.

Ø Low Range SOL Delay

Checks the SOL-Start of Line Delay

i) PLL tests Initialization.

1) Load CORRECTION LUT:

Correction=8000H (no correction),

Start of Line Delay = 0, 3FFH

no Expose Delay (4),

no Lock Delay (3).

2) Load Div_N for 87.5 Mhz frequency (Resolution=100).

3) Start Run ALU and Measure EXP_CLK2 -> CLK1.

Ø High Range Frequency

Checks PLL High Range frequencies (120-150 MHz).

i) PLL tests Initialization.

1) Load CORRECTION LUT:

no Correction (8000H),

no Start of Line Delay (0),

no Expose Delay (4),

no Lock Delay (3).

2) Load Div_N for each frequency.

3) Start Run ALU and Measure EXP_CLK2 -> CLK1.

Ø High Range Lock Delay

Checks Lock Delay

i) PLL tests Initialization.

1) Load CORRECTION LUT:

no Correction (8000H),

no Start of Line Delay (0),

no Expose Delay (4),

Lock Delay (3-511).

2) Load Div_N for 131.25 Mhz frequency (Resolution=150).

3) Start Run ALU and Measure EXP_CLK2 -> CLK1.

Ø High Range Expose Delay

Checks Expose Delay

i) PLL tests Initialization.

1) Load CORRECTION LUT:

no Correction (8000H),

no Start of Line Delay (0),

Expose Delay (4-255)

no Lock Delay (3).

2) Load Div_N for 131.25 Mhz frequency (Resolution=150).

3) Start Run ALU and Measure EXP_CLK2 -> CLK1.

Ø High Range Accumulation

Checks the Accumulative Correction factor

i) PLL tests Initialization.

1) Load CORRECTION LUT:

Correction=8000H (no correction), 4000H, C000H

no Start of Line Delay (0),

no Expose Delay (4),

no Lock Delay (3).

2) Load Div_N for 131.25 Mhz frequency (Resolution=150).

3) Start Run ALU and Measure EXP_CLK2 -> CLK1.

Ø High Range SOL Delay

Checks the SOL-Start of Line Delay

i) PLL tests Initialization.

1) Load CORRECTION LUT:

Correction=8000H (no correction),

Start of Line Delay = 0, 3FFH

no Expose Delay (4),

no Lock Delay (3).

2) Load Div_N for 131.25 Mhz frequency (Resolution=150).

3) Start Run ALU and Measure EXP_CLK2 -> CLK1.