Dolev 800 Field Service Diagnostics - The Test Tree - OMC
Card Ack Xilinx PC Interface WCS RAM Data RAM Communicate Analog Clocks Miscellan. INT. Pattern Spinner Spinner Ram
Checks all OMC Board Pc I/O address range (300H-30AH): When
this test fails, all OMC tests below do not execute in the batch.
Load Verify
Loads OMC.XIL file from the current directory to Xilinx.
Compares Xilinx data to the file data.
Once Mode Status Buf Message Buf Addr Counter Addr Decoder
Checks OMC Once Mode:
Activate BUS_HOST to '1'.
Disable 196 by creating pulse on DISABLE_196.
Check that DIS_READY is at '0'.
Activate BUS_HOST to '0'.
Checks the Status Buffer:
Activate BUS_HOST to '0'.
Activate LOAD_CNT to '1'.
Write to 302H, FC12H.
Activate LOAD_CNT to '0'.
Write to 300H, pattern.
Activate READ_STAT2 to '1'.
Read from 302H and compare to pattern.
Repeat (1) - (7) for different patterns.
Checks the Message Buffer:
PC data bus -> OMC data bus
OMC data bus -> PC data bus
Checks Address Counter.
Writing walking '1' data.
Writing walking '0' data.
Checks Address Decoder.
Activate SEL_RAMH to '0'.
Check WCS RAM Address range (0-FC00H).
Activate SEL_RAMH to '1'.
Check DATA RAM Address range (8000H-FC00H).
Check OMC I/O Address range (FC00H-FC0AH).
Data Bus Ramp Random Bytes I/O Load & Verify Check by 196 Verify by 196
Checks WCS RAM Data Bus.
Clear address counter.
Write pattern of data to address=0.
Clear address counter.
Read back and compare those data.
Checks WCS RAM Address Bus for stacked or shorted bits.
Checks WCS RAM by writing Ramp (address = data).
Checks WCS RAM by writing Random data.
Checks WCS RAM During Write/Read by Bytes only.
Loads and Verifies WCS:
Load OMC.WCS file from the current directory to WCS RAM.
Compare WCS data to the file data.
Checks WCS RAM by 196 Fast Access:
Write to Message Buffer (FC06H) data = 1155H.
Load special small OMC_MEM.WCS file to WCS RAM.
Verify WCS data to the file data.
Activate Fast Reset on 196 for test running.
Check WCS RAM using Ramp algorithm (start address 2200H).
Delay 1 second for test completion.
Read and Analyze Message Buffer:
Micro (196) Compares WCS data to OMC.WCS file data. Verify
process is the same as PC, described before. Because each reading from the WCS is the
opcode, the test takes too much time (50 sec.), so this test is not included in the short
batch. Fail on this test means that there was illegal writing to the WCS Code area, so
after the fail WCS is reloaded automatically and the next test execution might be
completed with Pass.
Data Bus Ramp Random Check by 196
Checks DATA RAM Data Bus.
Checks DATA RAM by writing Ramp (address = data).
Checks DATA RAM by writing Random data.
Checks DATA RAM by 196 Fast Access:
Write to Message Buffer (FC06H) data = 1155H.
Load special small OMC_MEM.WCS file to WCS RAM.
Verify WCS data to the file data.
Activate Fast Reset on 196 for test running.
Check WCS RAM using Ramp algorithm (start address 2200H).
Delay 1 second for test completion.
Read and Analyze Message Buffer:
Com3 Host A Com4 Host B PC <-> 196
Checks the serial RS232 port COM3 on OMC:
Write to POST (Pc) that COM3 is detected.
Enable COM3 serial port on OMC - wr_iob(FC0EH, 1H).
Check Default serial port registers values.
Enable Internal Transmit/Receive loopback.
Write to TRX buffer and compare to RCX buffer.
Write to RCX buffer and compare to TRX buffer.
Disable Internal Transmit/Receive loopback.
Disable COM3 serial port on OMC - wr_iob(FC0EH, 0H).
Checks the serial RS232 port COM4 on OMC:
Write to POST (Pc) that COM4 is detected.
Enable COM4 serial port on OMC - wr_iob(FC0EH, 2H).
Check Default serial port registers values.
Enable Internal Transmit/Receive loopback.
Write to TRX buffer and compare to RCX buffer.
Write to RCX buffer and compare to TRX buffer.
Disable Internal Transmit/Receive loopback.
Disable COM4 serial port on OMC - wr_iob(FC0EH, 0H).
Checks communication between PC and 196 microcontroller on
OMC, using the opcode algorithm which transfers parameters from PC to Micro, and receives
returned words form Micro to PC.
OMC Voltages Modulator
Checks the ability of the OMC board to measure analog
voltages.
Check for analog GND to be near zero.
Check for +5v power supply in range.
Checks Modulator values by writing PWM and DAC values.
Set PWM from 4 to 234 (DAC=671).
Measure modulator voltages from the OMC.
Analyze received voltages, by linear regression for gain,
offset and correlation problems.
Set DAC from 1 to 1020 (PWM=167).
Measure modulator voltages from the OMC.
Analyze received voltages, by linear regression for gain,
offset and correlation problems.
Overview 18 Mhz Sim. Expose Sim Sweep On
All frequencies are measured through 196 HSI port.
Checks 18432 Khz clock on the OMC Board.
Checks Simulated Expose clock.
Set SEL_SIM = 1 ; OMC_wr_196( FC1AH, bit 15 = 1).
Measure Simulated Expose clock [Hz] = 12000, Delta = 1.
Set SEL_SIM = 0 ; OMC_wr_196( FC1AH, bit 15 = 0).
Checks Simulated Sweep On clock.
Set SEL_SIM = 1 ; OMC_wr_196( FC1AH, bit 15 = 1).
Write to spinner counter ; OMC_wr_196( FC0AH, FDA8H).
Measure Simulated Sweep On clock [Hz] = 200, Delta = 1.
Set SEL_SIM = 0 ; OMC_wr_196( FC1AH, bit 15 = 0).
Startup Check 196 Wait State Extern. Int. CRC Chip 12C Chip
Perform Power Up (Start Up) test.
Reset 196 and activate Power Up test.
Analyze the only internal OMC errors.
Checks the Wait State working from Micro (196):
For the same time period read from specified address and
return number of reading loops.
Perform (1) for the address = FC00H (Wait State Enable).
Perform (1) for the address = F000H (Wait State Disable).
Compare number of loops (2) versus (3).
Checks that Micro (196) responses to the External Interrupt.
Use the special opcode which has been written by diagnostics.
No Interrupt occurred for interrupt mask = 0.
Interrupt occurred for all other interrupt mask patterns.
Checks the CRC Chip on OMC:
Reset the chip, Set and Reset again and Verify correct status.
Shifts different patterns and readback the signature.
Checks the I2C Chip on OMC:
Reset I2C by pulse on FE20H, bit 4.
Write patterns to I2C base address.
Readback those patterns with mask = 7FH (MSB is not
activated).
Enter and Verify Chip in Clock Mode.
Enter and Verify Chip in Normal Mode.
Enable I2C Chip Interrupt and check that:
Int. Grid Int. Slash Int. Diamond
Checks Internal Grid pattern generator on OMC by CRC.
Checks Internal Slash pattern generator on OMC by CRC.
Checks Internal Diamond pattern generator on OMC by CRC.
Spin Counter
Checks Spinner Counter.
Load Spinner Counter - OMC_wr_196( FC0AH, CACAH).
Verify that the data was really written - OMC_rd_196( FC0AH).
Enable manual operation (DIAG_CLOCK = '1').
Clear Spinner counter (pulse on SPIN_CLR).
Create 100 DIAG_CLOCK pulses and check that HSI0 pin was set.
Disable manual operation (DIAG_CLOCK = '0').
Clear Spinner counter (pulse on SPIN_CLR).
Check Spinner Frequency for different Spinner Counter
patterns.
Data Bus Address Bus Ramp Random Check by
196
Checks SPINNER RAM Data Bus.
Checks SPINNER RAM Address Bus for shorted and stacked bits.
Checks SPINNER RAM by writing Ramp (address = data).
Checks SPINNER RAM by writing Random data.
Checks SPINNER RAM by Micro.
Calculate and load Spinner Sin and Cos values (opcode).
Read and Verify the data.
