Dolev 800 Field Service Diagnostics -
The Test Tree - CRI

Card Ack
PC Buffer
Xilinx
Off Line
96 Periph
WCS RAM
SIM M.Step
Micro S. RAM
Phase CNT.
Real M.Step
Line Control
On Line
NVM

Card Ack

Checks all CRI Board Pc I/O address range (310H-31EH exclude 316H-317H): When this test fails, all CRI tests below do not execute in the batch.

PC Buffer

This test checks the buffers that separate between PC <-> 196. It is done with internal loop inside the buffers.

Xilinx

Load
Verify

Load

Loads CRI.XIL file from the current directory to Xilinx.

Verify

Compares Xilinx data to the file data. Uses the following files: CRI.XIL, 2018MASK.XIL

WCS RAM

Data Bus
Address Bus
Ramp
Random
Load & Verify
Code & Data
Verif by 196
12C Chip
Timer

Data Bus

Checks WCS RAM Data Bus:

1. Clear address counter.
   
2. Write pattern of data to address=0.
   
3. Clear address counter.
   
4. Read back and compare those data.

Address Bus

Checks WCS RAM Address Bus for stacked or shorted bits.

Ramp

Checks WCS RAM by writing Ramp (address = data).

Random

Checks WCS RAM by writing Random data.

Load & Verify

Loads and Verifies WCS:

1. Load CRI.WCS file from the current directory to WCS RAM.
   
2. Compare WCS data to the file data.

Code & Data

Checks WCS RAM by 196 Fast Access:

1. Write to Message Buffer (FFC0H) data = 1155H.
   
2. Load special small CRI_MEM.WCS file to WCS RAM.
   
3. Verify WCS data to the file data.
   
4. Activate Fast Reset on 196 for test running.
   
5. Check WCS RAM using Ramp algorithm from address 2200H to DBFFh Micro Checks from DC00 to FBFFh.
   
6. Delay 1.5 second for test completion.
   
7. Read and Analyze Message Buffer:
   
   1155H - Buffer not updated.
   2000H - Test was not completed.
   1234H - Test completed OK.
   xxxxH - The first bad address returned.

Verif by 196

Micro (196) Compares WCS data to CRI.WCS file data. Verify process is the same like from PC, described before. Because of each reading from the WCS is the opcode, the test takes too much time (50 sec.), so this test is not included in the short batch. Failure on this test means that there was illegal writing to the WCS Code area, so after the fail WCS is being reloaded automatically and the next test execution might complete with Pass.

12C Chip

Checks the I2C Chip on CRI:

1. Write patterns to I2C base address.
   
2. Readback those patterns with mask = 7FH (MSB is not activated).
   
3. Enter and Verify Chip in Clock Mode.
   
4. Enter and Verify Chip in Normal Mode.
   
5. Enable I2C Chip Interrupt and check that:
   
   I2C Chip responds to the Interrupt.
   Bus was released.
   Data was sent out from I2C.

Timer

Checks the 8254 timer:

1. Check Counter counting from 0-1000.
   
2. Check that the information supplied to the timer is correct.
   
3. Check 8 bit internal register by walking '1' patterns.
   
4. Check 8 bit internal register by walking '0' patterns.
   
5. Perform (1) - (4) for all three counters in the timer.

SIM M.Step

Sim Mstep
Sim Moving
Micro Step
ACC Request
Stop Cond

Sim Mstep

Checks that a simulated micro step (USTEPCLK) clock can be produced.

1. Generate EXT_SIM_USTEP and check for USTEPCLK.

Sim Moving

Checks that the MOVING signal can be reset and set.

Micro Step

Checks MICRO STEP clocks with six different N_DIV values. For each value the next steps are been done.

ACC Request

Checks accumulation clocks (ACC_LONG_REQ) with six different M_DIV values. N_DIV = 3.

Stop Cond

Checks Stop Condition signal (STOPCOND) with six different data address generator values.

Micro S. RAM

Sin & Cos RAMs
Polarity RAM
PLL Clock

Sin & Cos RAMs

Data Bus
Address Bus
Ramp
Random

Data Bus

Checks SIN&COS RAM Data Bus.

Address Bus

Checks SIN&COS RAM Address Bus for stacked or shorted bits.

Ramp

Checks SIN&COS RAM by writing Ramp (address = data).

Random

Checks SIN&COS RAM by writing Random data.

Polarity RAM

Data Bus
Address Bus
Ramp
Random

Data Bus

Checks POLARITY RAM Data Bus.

Address Bus

Checks POLARITY RAM Address Bus for stacked or shorted bits.

Ramp

Checks POLARITY RAM by writing Ramp (address = data).

Random

Checks POLARITY RAM by writing Random data.

PLL Clock

PLL Clocks
PLL Div Clk

PLL Clocks

Checks the pll frequency (PLL_CK) trough 8254 timer.

PLL Div Clk

Checks the pll divided frequency (DIV_PLL_CK) trough 8254 timer.

Phase CNT.

Mov By Phase
Real Time Ph

Mov By Phase

Checks MOVING signal with six different phase counter values.

Real Time Ph

Checks the PHASE_DET signal response.

Real M.Step

Micro Step
Acc Request
Stop Cond.

Micro Step

Checks Micro Step clock in real mode. Six different N_DIV value are loaded to generate USTEPCLK clock, the number of clocks in an 1 msec time interval are counted. The base clock is 10MHz from pll.

Acc Request

Checks ACC_LONG_REQ clock in real mode. Six different M_DIV value are loaded to generate USTEPCLK clock, the number of clocks in an 1 msec time interval are counted. The base clock is 10MHz from pll and n counter is program to 10.

Stop Cond.

Checks STOPCOND clock in real mode. Six different start values are loaded to generate USTEPCLK clock, the number of clocks in an 1 msec time interval are counted. The base clock is 10MHz from pll and n counter is program to 10.

Line Control

Line Clock
Expose Clock
Succ. Lines

Line Clock

Checks the LINECK (Line Xilinx) signal with different EOL (Line Xilinx) values.
*) Interval is 5 msec.

Expose Clock

Checks the EXPCK (Line Xilinx) signal with different SOL (Line Xilinx) values.
*) Interval is 5 msec.

Succ. Lines

Checks the EXPCK (Line Xilinx) signal with different SOL (Line Xilinx) values.
*) Interval is 50 * 5 msec.

On Line

PC <-> 196
Startup Check
Micro S. RAM
Analog Level

PC <-> 196

Checks communication between PC and 196 microcontroller on CRI, using the opcode algorithm which transfers parameters from PC to Micro, and receives returned words form Micro to PC.

Startup Check

Checks communication between PC and 196 microcontroller on CRI, using the opcode algorithm which transfers parameters from PC to Micro, and receives returned words form Micro to PC.

Micro S. RAM

Sin & Cos Ram
Polarity Ram

Sin & Cos Ram

Checks Sin&Cos Ram by Micro.

Polarity Ram

Checks Polarity Ram by Micro.

Analog Level

Sin Test
Cos Test
Mul Sin Test
Mul Cos Test
Extern. Int.
Driver Test

Sin Test

Checks the D/A by giving different digital values and then convert with the 196 A/D and compare.

Cos Test

Checks the D/A by giving different digital values and then convert with the 196 A/D and compare.

Mul Sin Test

Checks the D/A by giving different digital values and different analog values and then convert with the 196 A/D and compare.

Mul Cos Test

Checks the D/A by giving different digital values and different analog values and then convert with the 196 A/D and compare.

Extern. Int.

Checks that Micro (196) responses to the External Interrupt. Using the special opcode which has been written by diagnostics:

1. Generate the ACC_LONG_REQ and INDEX.
   
2. Check that the Micro responds to the interrupt.

Driver Test

Checks that the DRVR_ERROR~ signal from Port1.6 is set.
*) Note that if the STEPPER DRIVER board is defective test might fail.

NVM

Local Nvm
Destructive

Local Nvm

Checks the local NVM (EEPROM) and if possible with out programming it:

1. Check application init table crc if correct -> pass
   
2. Check random address above diag first add write & read if correct -> pass else fail.

Destructive

Checks the local NVM (EEPROM) and if possible with out programming it:

1. Writes and Reads ramp. (all addresses).