Dolev 800 Field Service Diagnostics -
The Test Tree - Strobe 5

Xilinx
Correct Lut
Micro Contro
PLL
Low Range
High Range
Integration
Cassettes
Drivers
Spinner Drv
PWR Convert

Xilinx

Load
Verify
Card Ack
Clocks
Stop Spiral

Load

Loads STROBE.XIL file from the current directory to Xilinx.

Verify

Compares Xilinx data to the file data. Uses the following files:
STROBE.XIL, 2018MASK.XIL 3030MASK.XIL

Card Ack

Checks all STROBE5 Board Pc I/O address range (280H-2BBH except 288H): When this test fails, all STROBE5 tests below do not execute in the batch. Because this function is realized in the Xilinx,
Pass/Fail of the test depends on loading success.

Clocks

Checks 20 Mhz clock and 8254 PIT:

1. 20 Mhz is divided in INTER Xilinx to:
   
   1Mhz -> CLK1
   1Khz -> CLK0
   1Khz -> CLK2
   
2. Signals OUT0 and OUT2 close GATE1, so Counter0 and Counter2 are been checked versus Counter1 (Window).

Stop Spiral

Checks the STOP SPIRAL circuit by simulation:

1. Reset ENC_ENB='0' to avoid STP_SPRL & END_STSPL from CRI.
   
2. Create CLRL to Reset STPSPRLL in INTER Xilinx.
   
3. Create SETSPIRALL to Set STPSPRLL.
   
4. Create CLRL to Reset STPSPRLL.

Correct Lut

Data Bus
Address Bus
Ramp
Random

Data Bus

Checks LUT RAM Data Bus.

Address Bus

Checks LUT RAM Address Bus for stacked or shorted bits.

Ramp

Checks LUT RAM by writing Ramp (address = data).

Random

Checks LUT RAM by writing Random data.

Micro Contro

Overview
Seq Adrs Bus
Proms ChkSum
Seq Data Bus
Seq Instruct
ALU Data Bus
ALU Register
ALU Instruct

Overview

All tests below activate diagnostics programs from the PROM's.

Seq Adrs Bus

Checks the Sequencer Address bus by single step:

1. Clear M(0-8) Counter in ALU_D Xilinx.
   
2. Increment the Counter by PCLK and Read the MEM(0-7) Bus.
   
3. Repeat (2) 255 times (ramp on MEM bus).

*)     Note that the Sequencer is not activated in this test.

Proms ChkSum

Checks PROMs checksum:

1. Disable Sequencer and Load MAP = 0 (for const. result from U807).
   
2. Load MEM addresses from 0-255.
   
3. Read PROM's data and calculate the checksum.

Seq Data Bus

Checks the Sequencer operation by single step:

1. Jump to the known MAP address.
   
2. Check that the sequencer address is OK.
   
3. Repeat (1) - (2) for 6 different patterns.

Seq Instruct

Checks the Sequencer ability to perform commands from PROM's:

1. Jump to the specific MAP address.
   
2. Activate sequencer in single step.
   
3. For each step analyze the sequencer address.

ALU Data Bus

Checks the ALU Data Bus via YB(0-15) bus:

1. Load data pattern to internal ALU register.
   
2. Readback and Verify the ALU register data.
   
3. Repeat (1) - (2) for different patterns.

ALU Register

Checks ALU internal registers (single step):

1. Write Ramp pattern to internal ALU registers.
   
2. Readback and verify registers through ALU Port B.
   
3. Readback and verify registers through ALU Port A.

ALU Instruct

Checks ALU logic and arithmetic operations:

1. Load LUT with the values which will be passed to internal reg's.
   
2. Perform addition operation (R0=R0+R1) until carry activating.
   
3. Perform XOR SUB and AND operations to registers.
   
4. Verify that no error occurs during above operations, by analyzing bits: ALU_F0~, ALU_F15~, CN_16 and ALUERR~

PLL

i) Initialization steps for all PLL tests:

1. Select PLL to desired frequency range.
   
2. Select 500KHz to PLL_REF via ENCLK CLK2.

Low Range

Normal
Lock Delay
Expose Delay

Normal

Checks PLL Low Range frequencies (45-130 MHz).
i)     PLL tests Initialization.

1. Load CORRECTION LUT:
   
   no Correction,
   no Start of Line Delay (0),
   no Expose Delay (4),
   no Lock Delay (3).
   
2. Load Div_N for each frequency.
   
3. Start Run ALU and Measure EXP_CLK2 -> CLK1.

Lock Delay

Checks PLL Start of Line operation.
i)     PLL tests Initialization.

1. Load CORRECTION LUT:
   
   no Correction,
   no Start of Line Delay (0),
   no Expose Delay (4),
   Lock Delay (3-511).
   
2. Load Div_N for 87.5 Mhz frequency (Resolution=100).
   
3. Start Run ALU and Measure EXP_CLK2 -> CLK1.

Expose Delay

Checks PLL Start of Line operation.
i) PLL tests Initialization:

1. Load CORRECTION LUT:
   
   no Correction,
   no Start of Line Delay (0),
   Expose Delay (4-255)
   no Lock Delay (3).
   
2. Load Div_N for 87.5 Mhz frequency (Resolution=100).
   
3. Start Run ALU and Measure EXP_CLK2 -> CLK1.

High Range

Normal
Lock Delay
Expose Delay

Normal

Checks PLL High Range frequencies (120-170 MHz).
i)     PLL tests Initialization:

1. Load CORRECTION LUT:
   
   no Correction,
   no Start of Line Delay (0),
   no Expose Delay (4),
   no Lock Delay (3).
   
2. Load Div_N for each frequency.
   
3. Start Run ALU and Measure EXP_CLK2 -> CLK1.

Lock Delay

Checks PLL Start of Line operation:
i)     PLL tests Initialization:

1. Load CORRECTION LUT:
   
   no Correction,
   no Start of Line Delay (0),
   no Expose Delay (4),
   Lock Delay (3-511).
   
2. Load Div_N for 131.25 Mhz frequency (Resolution=150).
   
3. Start Run ALU and Measure EXP_CLK2 -> CLK1.

Expose Delay

Checks PLL Start of Line operation:
i)     PLL tests Initialization:

1. Load CORRECTION LUT:
   
   no Correction,
   no Start of Line Delay (0),
   Expose Delay (4-255)
   no Lock Delay (3).
   
2. Load Div_N for 131.25 Mhz frequency (Resolution=150).
   
3. Start Run ALU and Measure EXP_CLK2 -> CLK1.

Integration

Overview
Omc - Strobe
Cri - Strobe
Power Suppl.
Data Voltage
Panel
Machine Exst
Com1<->Com2
Com3<->Com4

Overview

Checks Signals between Boards + External Devices.

Omc - Strobe

Creates DATA EXPOSE, SWEEP ON pulses on STROBE5 and measure them in OMC.
*) Note that there is blank region on the signal (without pulses), so the measuring has been done for 5 times until the expected result has been received. If after 5 times the result was not in the range, the last measuring has been displayed.

Cri - Strobe

Creates STOP_SPRL~ and END_SSP~ signals by CRI and checks the response to the STP_SPRRL~ signal on the STROBE5.

Power Suppl.

Checks all DOLEV 800 power supplies through the OMC board: +5v -5.2v +15v -15v +12v.

Data Voltage

Checks the voltages from DATA boards through the OMC board: +12v -12v +5v.

Panel

Checks Communication with panel and run panel Self Test Diagnostics.

Machine Exst

Checks if the mechanics and optics (machine) is connected to the Standard Controller:

1. Check if both Roller detectors are active -> illegal.
   
2. Check if both Carriage detectors are active -> illegal.
   
3. Check if both Cutter detectors are active -> illegal.
   
4. Check if the Laser is ON.
   
5. If 1-3 true then diagnostics conclusion - machine not exist.
   *) MECHANICS + OPTICS tests will be not executed in the batch.

Com1<->Com2

CPU Board Com1 <-> Com2 test via 504G34023 cable.

Com3<->Com4

OMC Board Com3 <-> Com4 test via "Uknown yet" cable.

Cassettes

CASSETTE #1
CASSETTE #2
CASSETTE #3

CASSETTE #1

Overview
Local Nvm
Destructive

Overview

Checks the CASSETTE #1
*) If Machine Exst test wasn't pass, then this test will not run in the batch

Local Nvm

Checks the local NVM (EEPROM). one byte programming:

1. Check the cassette existance by reading the detector.
   
2. Check application init char at address=0 expected=aa. if exist save data. generate random number x=[0-ff] write to address=x data=x, and read for verify.
   
3. If data at add=0 was aa restore data saved.

Destructive

Program ramp from address 0 to ff.

1. Check the cassette existance by reading the detector.
   
2. Writes and Reads ramp. (all addresses).

CASSETTE #2

Overview
Local Nvm
Destructive

Overview

Checks the CASSETTE #2
*) If Machine Exst test wasn't pass, then this test will not run in the batch

Local Nvm

Checks the local NVM (EEPROM). one byte programming:

1. Check the cassette existance by reading the detector.
   
2. Check application init char at address=0 expected=aa. if exist save data. generate random number x=[0-ff] write to address=x data=x, and read for verify.
   
3. If data at add=0 was aa restore data saved.

Destructive

Program ramp from address 0 to ff.

1. Check the cassette existance by reading the detector.
   
2. Writes and Reads ramp. (all addresses).

CASSETTE #3

Overview
Local Nvm
Destructive

Overview

Checks the CASSETTE #3
*) If Machine Exst test wasn't pass, then this test will not run in the batch

Local Nvm

Checks the local NVM (EEPROM). one byte programming.

1. Check the cassette existance by reading the detector.
   
2. Check application init char at address=0 expected=aa. if exist save data. generate random number x=[0-ff] write to address=x data=x, and read for verify.
   
3. If data at add=0 was aa restore data saved.

Destructive

Program ramp from address 0 to ff.

1. Check the cassette existance by reading the detector.
   
2. Writes and Reads ramp. (all addresses).

Drivers

RF Modulator
Relay Drv. 1
Relay Drv. 2
Stepper Drv.

RF Modulator

Checks the Rf Driver:

1. Increase Modulator Value from 0 to 10 Volts.
   
2. Check that the RF_LEVEL analog signal increases properly.

Relay Drv. 1

Checks that each Relay can be Set and Reset in 100msec duration.

Relay Drv. 2

Checks that each Relay can be Set and Reset in 100msec duration.

Stepper Drv.

Check the Stepper Driver clear signal:

1. Reset CLR_DRVR~ and Check after 1mSec that DRVR_ERROR~ is Clear.
   
2. Set CLR_DRVR~ and Check after 1mSec that DRVR_ERROR~ is Set.

Spinner Drv

9600 Rpm
12000 Rpm
13980 Rpm

9600 Rpm

Checks SIN_FDBK & COS_FDBK frequencies through the OMC for 9600 RPM.

12000 Rpm

Checks SIN_FDBK & COS_FDBK frequencies through the OMC for 12000 RPM.

13980 Rpm

Checks SIN_FDBK & COS_FDBK frequencies through the OMC for 13980 RPM.

PWR Convert

No Machine
With Machine

No Machine

Checks all functions of the driver exclude low power.

With Machine

Checks all functions of the driver.
Failure will occur when the test runs with no machine.