Serial Peripheral Interface (SPI)

Description | Theory of Operation | Wiring Diagrams

Description

The VLF satellite mother boards communicate with the main system microprocessor, located on the Master Processor Electronics (MPE) board, by a serial peripheral interface (SPI) cable. SPI signals are routed on 25-pin ribbon cables.

Several boards can be daisy-chained together on one cable, and address cards are inserted to create independent communication to each board. However, on the VLF Trendsetter the SPI cable (10-3529A) only goes from the backplane (10-1411D, J11) to the Engine Satellite Electronics (ESE) board (10-1426B, J3).

Due to the high speed of the signals on the SPI bus and the length of the bus cable, it is necessary to terminate the bus with a proper matching impedance. The SPI terminator (10-1310A) must always be connected to the output loop of the last satellite board in the SPI chain (the ESE board on the Trendsetter VLF). If the SPI chain is disconnected at some point for troubleshooting, the terminator has to be relocated to the new SPI terminus.

Note: For more information, see the SPI Terminator page.

Theory of Operation

This serial interface is comprised of the reset line SPI.RST, the satellite data line SPI.MOSI, the satellite data output line SPI.MISO, the data clock SPI.SCK, and eight address lines SPI.A0 to SPI.A7. All the signals are differential and conform to the EIA RS-485 party-line interface standard.

The SPI address space is allocated as follows:

• Bits 7-4 Satellite board select
• Bits 3-0 Register select

With this configuration, the SPI bus can accommodate a maximum of 16 satellite boards that may have up to 16 read/write registers.